It has been a trend to increase the packing density of a wafer. In order to achieve this, the dimension of devices must be scaled down to submicron range. Thus, the large integration of semiconductor integrated circuits (ICs) has been obtained by reduction in individual device size. Modern ICs interconnect literally millions of devices to perform a certain function. Due to improvements in the fabrication of ICs, two or more layers of interconnections between circuit elements are now used, and the number of active devices required to perform a given function has decreased. For example, some of the early DRAM memory cells required six transistors, whereas now one transistor and one capacitor suffice.
Typically, multilevel interconnections are formed in a chip in IC fabrication. In the formation of the ICs, it is critical to align a subsequent layer to a previous underlying layer. Alignment is the key way to make sure that a layer is aligned with an underlying layer. Alignment accuracy is considered how accurately the patterns of one level match their corresponding patterns on other levels. For contact etching, photoresist patterning or wafer deposition, there are several alignment marks per wafer. If one of the layers is misaligned, then a serious problem will arise in the chip. The accuracy of alignment process is a major factor that determines the yield of ICs. To achieve the necessary alignment precision, alignment marks are used. The alignment marks are typically incorporated into the chip or put in or on the edge of the wafer. The alignment mark is typically formed by etching a depth into a semiconductor wafer. The etching causes a pattern with step height in the wafer to act the alignment mark. One of the typical alignment marks is formed at the scribe lines of the wafer.
The alignment of one layer to the next is typically accomplished using a tool called wafer stepper. As is well known in the prior art, the wafer that has alignment marks formed therein is coated with a transparent photosensitive material, such as photoresist. The wafer is then loaded into the stepper. The stepper uses a laser beam with a fixed wavelength to sense the position of the alignment marks on the wafer by using the alignment marks as a reference point. The alignment mark is employed to adjust the position of the wafer to precisely align to the previous layer on the wafer. The interference from the alignment marks is reflected back to detecting devices in the stepper. The interference is also utilized as a signal to measure the exact position of the alignment marks.
The alignment mark pattern is typically patterned in the alignment area or scribe lines of the wafer. Subsequent layers used to form the integrated circuit are formed over the wafer. Subsequent layers will cover the original alignment mark pattern. The alignment mark is replicated in the subsequently formed layers. As more layers are added to the IC, the alignment mark pattern is propagated upward with subsequent layers. In some fabrication processes, a polishing process is needed to remove a portion of the inter-level dielectric (ILD) layer for achieving a better topography.
However, a problem associated with building up the alignment mark pattern is that it is incompatible with planarization process. It is necessary to planarize the topography of the IC for subsequently formed layer, such as metal layer. Thus, the replicated alignment mark in the interlevel dielectric layer is removed by the chemical mechanical polishing process. If a metal layer or a polysilicon layer is then formed on the ILD layer. Unfortunately, the replicated alignment mark in these layers is invisible, because the metal layer is opaque to the laser beam. Thus, it is impossible to align the metal pattern to contact pattern without the alignment mark pattern or a replicated alignment mark, it is impossible to align the metal pattern to contact pattern.
Prior art proposed non-zero alignment marks that are used in the back end of chemical mechanical polishing (CMP) process. However, the non-zero alignment mark must be created on each layer or only each oxide layer. Each alignment mark occupies one space on the wafer. Thus, it needs much space in the scribe lines or blank area for forming the non-zero alignment marks due to the ICs includes several metal layers. What is required is a method of alignment that can be used for chemical mechanical polishing.